1. Field of the Invention
The present invention relates to a switching device driving circuit for driving switching devices which are totem-pole connected between a high-potential power terminal and a low-potential power terminal.
2. Description of the Background Art
FIG. 1 is a block diagram showing a PWM inverter circuit of a three-phase bridge structure, which is generally employed for driving a motor 1 such as a three-phase brushless motor, for example. As shown in FIG. 1, three pairs of totem-pole connected power switching devices 2U and 2L, 3U and 3L and 4U and 4L are arranged in parallel between a high-potential power terminal P and a low-potential power terminal N. The power switching devices 2U, 2L, 3U, 3L, 4U and 4L are turned on/off by control signals from a control circuit 5.
FIG. 2 is a block diagram showing a portion of the control circuit 5 which is related to single-phase power switching devices 2U and 2L. In the circuit shown in FIG. 2, insulated gate bipolar transistors (hereinafter referred to as IGBTs) 6U and 6L are employed as the power switching devices 2U and 2L.
Referring to FIG. 2, an on/off command signal generating part 7 generates command signals for directing on/off of the IGBTs 6U and 6L, and supplies the same to an input terminal 8U of an upper arm of a high-voltage side and another input terminal 8L of a lower arm of a low-voltage side, respectively. The command signal received in the input terminal 8U is shifted up in level in a level shifting circuit 9 and inputted in a driving amplifier 10U to which a high source voltage V.sub.P is applied, while the command signal received in the input terminal 8L is directly inputted in a driving amplifier 10L, to which a low source voltage V.sub.N is applied. The level shifting circuit 9 may be prepared from a photocoupler 11, which is formed by a light emitting element 11a and a light receiving element 11b as shown in FIG. 4, for example. The command signal from the input terminal 8U is applied to the light emitting element 11a and the light receiving element 11b is connected to the high source voltage V.sub.P, thereby generating a command signal of a high-voltage level. The driving amplifiers 10U and 10L amplify the received command signals. The output of the driving amplifier 10U is applied to the gate of the upper arm IGBT 6U through a gate resistor R.sub.GU, while the output of the driving amplifier 10L is applied to the gate of the lower arm IGBT 6L through another gate resistor R.sub.GL.
FIG. 3 is a timing chart showing the on/off command signals which are applied to the input terminals 8U and 8L. Provided that the upper arm IGBT 6U and the lower arm IGBT 6L are simultaneously turned on, a short-circuit is caused across the high-potential power terminal P and the low-potential power terminal N and a large short-circuit current flows to the IGBTs 6U and 6L, so that the IGBTs 6U and 6L may be broken down. In order to prevent this, upper and lower arm dead times T.sub.R are provided between the on/off command signals which are applied to the input terminals 8U and 8L. To this end, the on/off command signal generating part 7 shown in FIG. 2 comprises a trigger signal generating part 7a and a dead time generating part 7b. The trigger signal generating part 7a produces signals in consideration of no upper and lower arm dead times T.sub.R, while the dead time generating part 7b provides the upper and lower arm dead times T.sub.R for the signals. These functions of the trigger signal generating part 7a and the dead time generating part 7b are implemented through a microcomputer, for example. Alternatively, the function of the trigger signal generating part 7a may be implemented by a microcomputer, while the function of the dead time generating part 7b may be implemented by a circuit such as a delay logic circuit.
In the conventional switching device driving circuit having the aforementioned structure, the upper and lower arm dead times T.sub.R must necessarily be provided between the on/off command signals for the upper and lower arms. Thus, processing for generating the on/off command signals is complicated, and the load for the microcomputer is significantly increased particularly in the case of high-frequency switching.
On the other hand, the time interval of the upper and lower arm dead times T.sub.R is determined depending on turn-on and turn-off times of the power switching devices and delay times of the driving amplifiers. The turn-on and turn-off times of the power switching devices are varied with the types and capacity of the power switching devices, or load conditions. It has been necessary to set the time interval of the upper and lower arm dead times T.sub.R, which is generally set at a fixed period, at the longest period determined under the worst condition. Further, disadvantageously, the upper and lower arm dead times T.sub.R must be re-set when the types of the power switching devices or the load conditions are changed.